參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 109/128頁
文件大小: 290K
代理商: MC68HC05G3
Page 71
Section 7: SERIAL PERIPHERAL INTERFACE (SPI)
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
DORD
x
Data transmission ORDer
When this bit is set, the data in the 8-bit shift register (SPDR
x) is shifted in/out
from the LSB. When this bit is cleared, the data in the SPDR
x is shifted in/out
from MSB.
This bit is cleared at reset.
0 - MSB first
1 - LSB first
MSTR
x
MaSTeR mode select
The MSTR
x bit determines whether the device is in master mode or slave mode.
In the master mode (MSTR
x = 1), SCKx pin is configured as the output pin and
the serial clock is generated by the internal clock generator when the CPU writes
to the SPDR.
In the slave mode (MSTR
x = 0), SCKx pin is configured as the input pin and the
serial clock is applied externally.
This bit is cleared at reset.
0 - slave mode
1 - master mode
BITS 3-1
Reserved
These bits are not used and are fixed to zero.
SPR
x
SPI
x clock rate select
This serial peripheral clock rate bit selects one of two bit rates of SCKx. This bit
is cleared at reset.
0 - Internal processor clock divided by 2
1 - Internal processor clock divided by 16
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