參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 81/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 46
MOTOROLA
Section 5: RESET/ INTERRUPT STRUCTURE
MC68HC05G3 (705G4) Specification Rev. 1.1
5.1.1
SOFTWARE INTERRUPT (SWI)
SWI is an executable instruction rather than a prioritized asynchronous interrupt source. In
a sense, it is lower in priority than any source because once any interrupt sequence has
begun, SWI cannot override it. In another sense, it is higher in priority than any sources
except reset because once the SWI opcode is fetched, no other sources can be honored
until after the first instruction in the SWI service routine has been executed. The interrupt
service routine address is specified by the contents of memory locations $FFFC and
$FFFD. SWI causes the I mask bit in the CC register to be set.
5.2
INTERRUPTS OF THE MC68HC05G3 (705G4)
The HC05G3 (705G4) has six hardware interrupt sources: IRQ1 and IRQ2, key wakeup
interrupt (KWI), timer 1 (TOI, ICI, OC1I), timer 2 (TI2I, OC2I), serial transfer complete
interrupt (SPI1 and SPI2), and time base interrupt (TBI).
5.2.1
IRQ1/IRQ2
The two interrupt request inputs, IRQ1 and IRQ2, share same the vector address at $FFFA
and $FFFB.
Two IRQ1S and IRQ2S bits in the interrupt control register (INTCR) control two IRQs,
respectively, so that IRQ1 and IRQ2 respond only to the falling edge or falling edge and low
level at the pin. IRQ1 and IRQ2 are enabled by IRQ1E and IRQ2E bits and IRQ1F and
IRQ2F bits are provided in the interrupt status register (INTSR).
IRQ1 and IRQ2 pins are shared with PC7 and PC6 and the IRQ
x pin states can be
determined by reading port C pins when DDRC7/6 = 0. The BIL and BIH instructions are
only effective for the IRQ1 input.
When DDRC7/6 =1, the IRQ
xF can be set by the data latch. Therefore, care must be taken
to ensure the flag is cleared by software before the IRQ
xE bit is enabled.
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