參數(shù)資料
型號(hào)： MC68HC05G3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 37/128頁
文件大?。?/td> 290K
代理商： MC68HC05G3
Page 6
MOTOROLA
Section 1: INTRODUCTION
MC68HC05G3 (705G4) Specification Rev. 1.1
1.4
SYSTEM CONFIGURATIONS
The MC68HC05G3 (705G4) has several options. The sections below describe oscillator
clocks, time base, and I/O pin configurations.
1.4.1
OSCILLATORS AND CLOCK DISTRIBUTIONS
There are two oscillator blocks: OSC and XOSC. Several combinations of the clock
distributions are allowed for the modules in the MC68HC05G3 (705G4). Refer to the
following block diagram.
Figure 1-5: Clock Signal Distribution
1.4.1.1
OSC ON LINE
The main oscillator (OSC) can be stopped to conserve power via the STOP instruction or
the FOSCE bit in the MISC register. The effects of restarting the OSC will vary depending
on the current state of the MCU, including SYS0:1 and FOSCE.
If XOSC is not used, XOSC1 should be connected to either Vss or Vdd.
If OSC is the system clock, FOSCE should remain 1. Executing the STOP instruction in this
condition will halt OSC, put the MCU into a low-power mode and clear the 6-bit power-on
delay (POD) counter. The 7-bit divider is not initialized. Exiting STOP with external IRQ or
reset re-starts the oscillator. When the POD counter overflows, internal reset is released
and execution can begin. The stabilization time will vary between 8064 and 8192 counts.
NOTE:
Exiting STOP with external reset will always return the MCU to the states
defined by the register definitions, such as SYS0:1=0:0, FOSCE=1.
XOSC1
XOSC2
STOP
OSC1
OSC2
1/20
1/21
1/25
SYS1 SYS0
SEL
1/2
OSC DIVIDER
(7bit)
OSC
XOSC
CLK
CTRL
POD
(6bit)
TIMEBASE
TIMER2
TIMER1
SPI1
CPU
WAIT
EXCLK
1/20
1/27
XCLK
SPI2
A/D
PWM
PORTS
SYSTEM
CLOCK
FTUP
FOSCE/
PWRON
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