參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 44/128頁
文件大小: 290K
代理商: MC68HC05G3
Page 12
MOTOROLA
Section 1: INTRODUCTION
MC68HC05G3 (705G4) Specification Rev. 1.1
Table 1-3: TB Interrupt Frequency
COP
The computer operating properly (COP) watchdog timer is controlled by the
COPE and COPC bits in the TBCR2 register.
The COP uses the same clock as TBI that is selected by the TBR1 and TBR0
bits. The TBI is divided by four and overflow of this divider generates COP
timeout reset if the COP enable (COPE) bit is set. The COP timeout reset has
the same vector address as POD and external RESET. To prevent the COP
timeout, the COP divider is cleared by writing a one to the COP clear (COPC)
bit.
When the time base divider is driven by the OSC clock, the clock for the
divider is suspended during stop mode or when FOSCE is 0. This may cause
COP period stretching or no COP timeout reset when processing errors
occur. To avoid these problems, it is recommended that XOSC clock be
used for the COP functions.
When the time base (COP) divider is driven by the XOSC clock, the divider
does not stop counting and the COPC bit must be triggered to prevent the
COP timeout.
Table 1-4: COP Timeout Period
TBR1
TBR0
DIVIDE RATIO
FREQUENCY (HZ)
OSC=
4.0M
OSC=
4.1943M
XOSC=
32.768K
0
1
0
1
0
1
TBCLK DIVIDED BY 128
TBCLK DIVIDED BY 4096
TBCLK DIVIDED BY 8192
TBCLK DIVIDED BY 16,384
244
7.63
3.81
1.91
256
8.00
4.00
2.00
256
8.00
4.00
2.00
TBR1
TBR0
0
1
0
1
0
1
12.3
393
786
1573
16.4
524
1048
2097
11.7
375
750
1500
15.6
500
1000
2000
11.7
375
750
1500
15.6
500
1000
2000
MIN
MAX
OSC=4.0MHz
OSC=4.1943MHz
XOSC=32.768KHz
MIN
MAX
MIN
MAX
COP PERIOD (MILLI-SECOND)
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