參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 23/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
MOTOROLA
Chapter 2. Transmitter
2-5
Functional Description
2.3
Functional Description
The transmitter takes the data byte presented at its data input, creates a transmission
character using its 8B/10B encoder and serially transmits the character out of the
differential link output pads. The following sections provide a detailed description of the
transmitter and its modes of operation.
2.3.1
Transmit Data Input Register Operation
The transmit data input register accepts data to be transmitted and synchronizes it to the
internal clock domain. Transmit data is normally uncoded 8-bit data, however, transmission
of pre-coded 10-bit data is supported in Ten-Bit Interface (TBI) mode. TBI mode is enabled
by asserting TBIE high.
The transmit data interface is a Double Data Rate (DDR) interface; the data is sampled and
stored on the rising and falling edges of the transmit interface clock XMIT_x_CLK. There
are several clocking options on the transmit data interface that are described in Section
2.3.1.1
Transmitting Uncoded Data
Uncoded data is presented in 8-bit bytes to the input register through the XMIT_x_7–
XMIT_x_0 signals. The uncoded data is coded into 10-bit transmission characters using an
on-chip 8B/10B encoder. 8B/10B coding ensures DC balance across the link and sufficient
transition density to facilitate reliable data recovery. The XMIT_x_7–XMIT_x_0 signals
are interpreted as data when the XMIT_x_K signal is low.
The 8B/10B code includes special control codes. Special control codes may be transmitted
by asserting XMIT_x_K high, and XMIT_x_IDLE high as indicated in Table 2-2. The
transmit byte is assumed to be a control code in this state.
The transmitter generates an Idle character (K28.5) when XMIT_x_K is high and
XMIT_x_IDLE is low as indicated in Table 2-2. An Idle character of proper running
disparity is generated when this state is asserted; the state on the XMIT_x_7–XMIT_x_0
signals are ignored. This eases generation of Idle characters needed for byte and word
synchronization and allows the link to maintain alignment when transmission of data is not
needed.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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