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參數(shù)資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 62/104頁 |
| 文件大小： | 1595K |
| 代理商： | MC92610VF |
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5-4
MC92610 SERDES User’s Manual
MOTOROLA
System Accessible Test Modes
5.2.1
Loop Back System Test
The MC92610 can be configured in loop back mode where the transmitted data is looped
back to its receiver independent of the receiver’s link inputs. This is enabled by setting LBE
high. The characters transmitted are controlled by the normal transmitter controls. If the
transceiver is working properly, the data/control characters transmitted are received by the
receiver. This allows system logic to use various data sequences to test the operation of the
transceiver.
The data is looped back though the primary link path if XCVR_x_RSEL is low and through
the redundant path if XCVR_x_RSEL is high.
The loop-back signals are electrically isolated from the XLINK0/1_x_P or XLINK0/1_x_N
output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back
signals still operate normally. When in loop-back mode, the LBOE signal controls the
action of the selected link output signals. When LBOE is low, the XLINK0_x_P /
XLINK1_x_P or XLINK0_x_N / XLINK1_x_Noutput signals are undriven and are
high-impedance. When LBOE is high, the link output signals enabled by XCVR_x_RSEL
continue to operate normally.
The receiver’s link input signals, RLINK0_x_P / RLINK1_x_P and RLINK0_x_N /
RLINK1_x_N, are electrically isolated during loop back mode, such that their state does
not affect the loop back path.
5.2.2
BIST Sequence System Test Mode
The MC92610’s transmitter has an integrated, 23rd order, Pseudo-Noise (PN) pattern
generator. Stimulus from this generator may be used for system testing. The receiver, has a
23rd order signature analyzer that is synchronized to the incoming PN stream and may be
used to count character mismatch errors relative to the internal PN reference pattern.
This implementation of the 23-bit PN generator and analyzer uses one of the two the
polynomials depending on the state of BIST_MODE_SEL:
PN Equation 1: f = 1 + x5 + x23 (BIST_MODE_SEL asserted low)
PN Equation 2: f = 1 + x18 + x23 (BIST_MODE_SEL asserted high)
When inter-operating with Motorola’s 1.25 Gbaud SERDES devices (MC92600 or
MC92602) use PN equation 1. PN equation 2 is meant for use with external test equipment
Low
High
Loop back BIST sequence system test mode.
High
Don’t care
Reserved.
Table 5-4. Test Mode State Selection
TST_1
TST_0
LBE
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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