參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 86/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
7-8
MC92610 SERDES User’s Manual
MOTOROLA
MC92610 Chip Pinout Listing
XMIT_C_5
Transmitter C, Data bit 5
B5
Input
HSTL
XMIT_C_6
Transmitter C, Data bit 6
A4
Input
HSTL
XMIT_C_7
Transmitter C, Data bit 7
C5
Input
HSTL
XMIT_C_K
Transmitter C, Special Character (Data bit 8
for TBI mode)
D6
Input
HSTL
XMIT_C_IDLE
Transmitter C, Idle Enable Bar, (Data bit 9 for
TBI mode)
C6
Input
HSTL
XMIT_C_CLK
Transmitter C, Transmit Interface Clock
D8
Input
HSTL
RECV_C_0
Receiver C, Data bit 0
E1
Output
HSTL
RECV_C_1
Receiver C, Data bit 1
G4
Output
HSTL
RECV_C_2
Receiver C, Data bit 2
F3
Output
HSTL
RECV_C_3
Receiver C, Data bit 3
F2
Output
HSTL
RECV_C_4
Receiver C, Data bit 4
F1
Output
HSTL
RECV_C_5
Receiver C, Data bit 5
H4
Output
HSTL
RECV_C_6
Receiver C, Data bit 6
G2
Output
HSTL
RECV_C_7
Receiver C, Data bit 7
G1
Output
HSTL
RECV_C_K
Receiver C, Special Character (Data bit 8 for
TBI mode)
J4
Output
HSTL
RECV_C_9
Receiver C, Data bit 9 for TBI mode
H3
Output
HSTL
RECV_C_IDLE
Receiver C, Idle Detect
H1
Output
HSTL
RECV_C_ERR
Receiver C, Error Detect
J2
Output
HSTL
RECV_C_CLK
Receiver C, Receive Data Clock
H2
Output
HSTL
XCVR_C_RSEL
Transceiver C, Redundant Link Select
T13
Input
CMOS
XCVR_C_DISABLE
Transceiver C, Disable
B14
Input
CMOS
RLINK_C0_P
Receiver C, Primary Positive Link Input
H17
Input
Link
RLINK_C0_N
Receiver C, Primary Negative Link Input
G17
Input
Link
RLINK_C1_P
Receiver C, Redundant Positive Link Input
H15
Input
Link
RLINK_C1_N
Receiver C, Redundant Negative Link Input
G15
Input
Link
XLINK_C0_P
Transmitter C, Primary Positive Link Out
F18
Output
Link
XLINK_C0_N
Transmitter C, Primary Negative Link Out
E18
Output
Link
XLINK_C1_P
Transmitter C, Redundant Positive Link Out
F16
Output
Link
XLINK_C1_N
Transmitter C, Redundant Negative Link Out
E16
Output
Link
XMIT_D_0
Transmitter D, Data bit 0
B7
Input
HSTL
XMIT_D_1
Transmitter D, Data bit 1
C8
Input
HSTL
Table 7-2. 324 MAPBGA Signal to Ball Mapping (continued)
Signal Name
Description
Ball Number
(324 MAPBGA)
Direction
I/O Type
F
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e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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