參數(shù)資料
型號(hào)： MC92610VF
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝： 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁(yè)數(shù)： 49/104頁(yè)
文件大?。?/td> 1595K
代理商： MC92610VF
MOTOROLA
Chapter 4. System Design Considerations
4-1
Chapter 4
System Design Considerations
This chapter describes the system design considerations for the MC92610, including clock
configuration, device startup and initialization, and proper use of repeater mode.
4.1
Reference Clock Configuration
The clock inputs REF_CLK_P and REF_CLK_N are the differential reference clock inputs
for the MC92610. The frequency of the clock signal applied to these inputs along with the
settings on the configuration inputs determine the speed at which the serial links operate.
Also, the legal ranges of reference clock frequencies vary depending on the configuration
selected. Table 4-1 shows the ranges allowed for each configuration.
NOTE
The device must be reset by setting RESET low, if the reference
clock configuration is changed after power-up.
The clock inputs REF_CLK_P and REF_CLK_N are normally driven with a differential
clock source. However, the reference clock may also be driven with a single-ended source.
In this situation, the REF_CLK_P signal is driven by the single-ended clock source and the
REF_CLK_N signal is held at the HSTL reference voltage as defined in Section 6.2. The
Table 4-1. Legal Reference Clock Frequency Ranges
HSE
LME
DDRE
Reference
Frequency Min
(MHz)
Reference
Frequency Max
(MHz)
Link Transfer Rate
(Gigabaud)
Low
reserved
Low
High
95.00
156.25
1.900 - 3.125
Low
High
Low
95.00
156.25
1.900 - 3.125
Low
High
47.50
78.125
1.900 - 3.125
High
Low
reserved
High
Low
High
47.50
78.125
0.950 - 1.5625
High
Low
47.50
78.125
0.950 - 1.5625
High
23.75
39.0625
0.950 - 1.5625
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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