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參數(shù)資料
| 型號(hào)： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 25/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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MOTOROLA
Chapter 2. Transmitter
2-7
Functional Description
Data on the transmitter A interface is sent first, followed by transmitter B. Data on the
transmitter C is sent first, followed by transmitter D.
Link Multiplexer mode is enabled by asserting LME high.
2.3.1.4
Repeater Mode
Repeater mode configures the MC92610 into a 4-link receive-transmit repeater. In this
mode, the data to transmit is obtained from its receiver (transmitter A gets receiver A’s data,
transmitter B gets receiver B’s data, and so on). The transmit input signals, XMIT_x_7 -
XMIT_x_0, XMIT_x_K and XMIT_x_IDLE are ignored. Repeater mode is enabled by
asserting REPE high. See Section 3.3.9 for more information on Repeater mode.
2.3.1.5
Transmit Interface Clock Configuration
The transmitter data interface operates at high frequency (up to 156.25MHz). In order to
ease development of devices that interact with the MC92610, all of its data interfaces are
source-synchronous. The data for each transmitter has its own dedicated clock input. This
allows the clock at the source of the data to be routed with the data ensuring matched delay
and timing. However, if per-transmitter clock sources are not available or deemed
unnecessary, all transmitters may be clocked by a common clock source. This is enabled by
asserting XMIT_REF_A high. When XMIT_REF_A is high, the XMIT_A_CLK becomes
the interface clock for all active transmitters.
The transmit interface clock inputs, XMIT_x_CLK, and the PLL reference clock,
REF_CLK_P/REF_CLK_N, inputs must be operated at exactly the same frequency.
However, there may be an arbitrary initial phase relationship between the PLL reference
clock and the transmit interface clocks. The phase relationship between the transmit
interface clock and the PLL reference clock is established after the internal PLL locks.
Once locked, the transmit data interface tolerates +180o of transmit interface clock phase
drift relative to the PLL reference clock.
Additionally, all of the MC92610’s data interfaces are DDR, except in Link Multiplexer
mode. DDR interfaces, in which the data is sampled and stored on the rising and falling
edges of the clock, reduces the clock frequency by 50 percent while maintaining
throughput.
The configuration assertings of the MC92610 affect the legal range of clock frequencies at
which it may be operated. Section 4.1, Table 4-1 shows legal transmit interface clock
frequencies for all modes of operation.
2.3.1.6
8B/10B Encoder Operation
The 8B/10B Encoder encodes 8-bit data/control from the input register into 10-bit
transmission characters. The ANSI standard for Fibre Channel 8B/10B coding standard is
followed [1,2]. Running disparity is maintained and the appropriate transmission characters
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For More Information On This Product,
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