參數(shù)資料
型號: MC92610VF
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封裝: 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324
文件頁數(shù): 43/104頁
文件大?。?/td> 1595K
代理商: MC92610VF
MOTOROLA
Chapter 3. Receiver
3-13
Receiver Functional Description
3.3.5
8B/10B Decoder
The 8B/10B decoder takes the 10-bit character from the Transition Tracking Loop and
decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of
error checking. First it checks that all characters are a legal member of the 8B/10B coding
space. The decoder also checks for running disparity errors. If the running disparity exceeds
the limits set in the 8B/10B coding standard then a disparity error is generated.
NOTE
8B/10B coding is meant only to improve data transmission
characteristics and is not a good error detection code. Many
8B/10B characters alias to other valid 8B/10B characters in the
presence of bit errors. Error detection and correction
techniques must be applied outside of MC92610 if better than
10-12 bit error rate is required.
An illegal character or disparity error sets the RECV_x_ERR signal high, coincident with
the received data for one byte output period. The “Code Error” or “Disparity Error” is
reported as described in Section 3.3.6.3. It is difficult to determine the exact byte that
causes a disparity error, so the error should not be associated with a particular received byte.
It is rather a general indicator of the improper operation of the link. Its intended use is for
the system to monitor link reliability.
The 8B/10B decoder is bypassed when operating in TBI mode (TBIE set high.)
3.3.6
Receiver Interface
The receiver interface facilitates transfer of received data to the system. It also provides
information on the status of the link. Table 3-1 describes each of the signals involved in
receiver operation.
The receiver interface, through which received data is obtained, may be operated in Byte
mode or in TBI mode. There are several timing mode options for the receiver interface.
Each of the operating modes are described below.
Half-Speed Enable
HSE
n/a
Does not affect word synchronization.
Double Data Rate
DDRE
n/a
Does not affect word synchronization.
Table 3-2. Word Synchronization States (continued)
Mode
Signals
Recommended
State
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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