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參數(shù)資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 34/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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MOTOROLA
Chapter 3. Receiver
3-5
Receiver Functional Description
3.3
Receiver Functional Description
The MC92610 receiver is based upon an oversampled transition tracking loop data recovery
method. The receiver receives differential data in one of two operating ranges. It may be
operated in full rate range with a maximum data rate of 2.5 Gbps (3.125 gigabaud) or at
half-rate at 1.25 Gbps (1.5625 gigabaud). The operating range is determined by the state of
the HSE input.
The received serial data is accumulated into ten-bit characters. The ten-bit characters are
forwarded to the 8B/10B decoder where the original data is obtained. Alternately, the
decoder can be bypassed and the ten-bit character is forwarded to the receiver interface in
ten-bit interface (TBI) mode.
REF_CLK_P/N
PLL Reference Clock
PLL input reference clock. Provides
reference frequency for the receiver
interface when Recovered Clock mode
is disabled (RCCE is low).
Input
-
ADIE
Add/Delete Idle Enable
Indicates that the receiver is free to
add/delete Idle characters to/from the
output data stream to maintain
alignment.
Input
High
REPE
Repeater Mode Enable
When enabled, the transmitter obtains
transmit data from the receiver.
Input
High
TST_0/
TST_1
Test Mode
Indicates operating/test mode of the
chip.
Input
-
RLINK_x0_N/
RLINK_x0_P
Link Serial Receive Data,
Primary Links
Differential serial receive data input
pads for the primary links.
Input
-
RLINK_x1_N/
RLINK_x1_P
Link Serial Receive Data,
Redundant Links
Differential serial receive data input
pads for the redundant links.
Input
-
Internal Signals
rx_clock
High Speed Transceiver
Clock
Internal, differential high speed clock
used to transmit and receive link data.
Input
-
recv_a_clk
Receiver A Interface
Clock
Internal copy of receiver A’s interface
clock.
Input
-
loop_back_data
Loop Back Data
Differential loop back receive data.
Input
-
link_mux_data
Link Multiplexer Mode
Data
Received data from adjacent receiver to
direct to receiver interface when in Link
Multiplexer mode (LME is high.)
Input
-
repeat_data
Received Repeat Data
Repeater mode, received data to
re-transmit.
Output
-
Table 3-1. Receiver Interface Signals (continued)
Signal Name
Description
Function
Direction
Active
State
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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