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參數(shù)資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 37/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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3-8
MC92610 SERDES User’s Manual
MOTOROLA
Receiver Functional Description
Loop-back data is processed the same as normally received data. Loop-back enables
at-speed self-test to be implemented for production test and for in-system self-test. The
loop-back signals are electrically isolated from the link input signals. Therefore, if the
inputs are shorted, open, or otherwise disturbed, the loop-back signals still operate
normally.
See Section 5.2 for more information on system accessible test modes.
3.3.2
Transition Tracking Loop and Data Recovery
The received differential data from the input amplifier is sent to the transition tracking loop
for data recovery. The MC92610 uses an oversampled transition tracking loop method for
data recovery. The differentially received data is sampled and processed digitally providing
for low bit error rate (better than 10-12) data recovery of a distorted bit stream.
The transition tracking loop is tolerant of frequency offset between the transmitter and
receiver. The MC92610 reliably operates with +100 ppm of frequency offset. The transition
tracking loop synthesizes a recovered clock that matches the frequency of the received data.
Recovered data is accumulated into 10-bit characters. Characters are aligned to their
original 10-bit boundaries if a Byte Alignment mode is enabled.
3.3.3
Byte Alignment
The receiver supports the alignment of accumulated bits to their original transmitted
character boundaries through Idle character recognition. Byte alignment is supported in
Byte and TBI interface modes. Byte alignment is enabled by asserting BSYNC high.
3.3.3.1
Byte Alignment and Realignment Method
At power-up, the receiver starts an alignment procedure, searching for the 10-bit pattern
defined by the 8B/10B Idle code. Alignment logic checks for the distinct Idle pattern,
‘0011111010’ and ‘1100000101’ (ordered bit 0 to bit 9), characteristic of the K28.5 Idle
pattern. The search is done on the 10-bit data in the receiver, and is therefore independent
being in Byte or TBI mode. Alignment requires a minimum of four, error-free, received Idle
characters to ensure proper alignment and lock. Non-Idle characters may be interspersed
with the Idle characters. The disparity of the Idle characters is not important to alignment
and can be positive, negative or any combination.
The receiver begins data flow of received characters once alignment is established and
locked. However, if word synchronization is enabled, received characters do not flow to the
receiver interface until word synchronization is established. Alignment remains locked
until any one of three events occur that indicate loss of alignment:
Alignment is lost when a misaligned Idle sequence is detected. A misaligned Idle
sequence is defined as four Idle characters with an alignment different than the
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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