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參數(shù)資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 54/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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MOTOROLA
Chapter 4. System Design Considerations
4-5
Power Supply Requirements
4.5
Power Supply Requirements
The recommended board for the MC92610 has a minimum of two solid planes of one ounce
copper. One plane is to be used as a ground plane and the second plane is to be used for the
1.8V supply. It is recommended that the board has its own 1.8V and 1.5V regulators with
less than 50mV ripple.
4.6
Phase Locked Loop (PLL) Power Supply Filtering
An analog power supply is required. The TX_PLLVDD signal provides power for the
analog portions of the PLL. To ensure stability of the internal clock, the power supplied to
the PLL is filtered using a circuit similar to the one shown in Figure 4-1. For maximum
effectiveness, the filter circuit is placed as close as possible to the TX_PLLVDD ball to
ensure it filters out as much noise as possible. The ground connection should be near the
TX_PLLVDD ball. The 0.003mF capacitor is closest to the ball, followed by the 1 mF
capacitor, and finally the 1 W resistor to Vdd on the 1.8V power plane. The capacitors are
connected from TX_PLLVDD to the ground plane. Use ceramic chip capacitors with the
highest possible self-resonant frequency. All traces should be kept short, wide and direct.
TBIE
Ten-Bit Interface Enable
Device must be reset.
HSE
Half-Speed Enable
Device must be reset.
DDRE
Double Data Rate Enable
Device must be reset.
BSYNC
Byte Synchronization Mode
Device must be reset.
ADIE
Add/Drop Idle Enable
Device must be reset.
REPE
Repeater Mode Enable
Device must be reset.
LME
Link Multiplexer Mode
Device must be reset.
RCCE
Recovered Clock Enable
Device must be reset.
WSE
Word Synchronization Enable
Device must be reset.
LBE
Loop Back Enable
Receiver must acquire new bit phase
alignment; byte and word synchronization
must be re-established.
LBOE
Loop Back Output Enable
No action required.
RESET
System Reset Bar
Device is reset.
Table 4-3. Asynchronous Configuration and Control Signals (continued)
Signal Name
Description
Effect of Changed State
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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