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| 型號(hào)： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 32/104頁 |
| 文件大小： | 1595K |
| 代理商： | MC92610VF |
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MOTOROLA
Chapter 3. Receiver
3-3
Receiver Interface Signals
“D.” Internal signals are not available at the I/O of the device, but are presented to illustrate
device operation.
Table 3-1. Receiver Interface Signals
Signal Name
Description
Function
Direction
Active
State
RECV_x_7 through
RECV_x_0
Received Byte
Received and decoded data/control
byte.
The least significant 8 bits of received
data in TBI mode.
Output
-
RECV_x_K
Special Data Indicator/
Received Bit 8
Indicates that received byte is a special
control byte.
Received bit 8 in TBI mode.
Errors are coded using this signal. See
Section 3.3.6.3 for error codes.
Output
-
RECV_x_9
Received Bit 9
Received bit 9 in TBI mode. Unused in
8-bit mode.
Output
-
RECV_x_IDLE
Receiver Idle Detect
Indicates that the receiver detected an
Idle character (operates in Byte and TBI
modes).
Errors are coded using this signal. See
Section 3.3.6.3 for error codes.
Output
-
RECV_x_ERR
Receiver Error
Indicates that the receiver detected an
error. RECV_x_IDLE and RECV_x_K
must be decoded to determine error
condition. See Section 3.3.6.3 for error
codes.
Output
-
RECV_x_CLK
Receiver Interface
Clock
Clock used for clocking receiver
interface. Source and frequency of this
clock depend on operating mode. See
Section 4.1 for more information.
Output
-
DROP_SYNC
Drop Synchronization
Indicates that the current byte and word
alignment should be invalidated and new
alignment acquired. DROP_SYNC is
level sensitive and not synchronized to a
clock, it must be asserted for at least two
clock periods.
Input
High
XCVR_x_DISABLE Transceiver Disable
Indicates that the transmitter and
receiver for this transceiver are disabled.
Input
High
XCVR_x_RSEL
Transceiver Link Select
Indicates that the redundant link inputs
are observed and that primary link
inputs are ignored.
Input
High
RECV_EQ_EN
Receive Equalization
Enable
Indicates that receiver equalization is
enabled and that high frequency gain is
applied to the received signal.
Input
High
TBIE
Ten-Bit Interface Enable Indicates that the receiver interface is in
ten-bit mode and that the 8B/10B
decoder is bypassed.
Input
High
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