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參數資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數： | 53/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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4-4
MC92610 SERDES User’s Manual
MOTOROLA
Configuration and Control Signals
4.3.5
Reference Clock Timing Mode
Repeater mode is timed exclusively to the reference clock domain as stated above. A
frequency offset between the source transmitter and the repeater will cause the repeater’s
receiver to eventually overrun/underrun. To ensure that overrun/underrun does not cause
data to be lost, add/drop idle mode must be used. Add/drop idle mode is enabled by setting
ADIE high. The repeater adds or drops Idles from the data stream to maintain alignment to
the reference clock. The guidelines for Idle density are discussed in Section 4.3.2.
4.3.6
Half-Speed Mode, Double Data Rate Mode
Half-speed mode and double data rate mode simply affect the frequency of the reference
clock that must be provided and the timing of the receiver interface. All combinations of
these modes are supported in repeater mode. See Section 3.3.8 for more information on
half-speed mode and Section 3.3.6 for more information on double data rate mode.
4.4
Configuration and Control Signals
MC92610 has many configuration and control signals that are asynchronous to all inputs
clocks. Most of the signals affect internal configuration state and must be set at power-up.
If their state is changed after power-up, some require that the chip be reset by setting
RESET_B low and then releasing high. While other configuration signals are meant to be
changed during normal operation and do not require chip reset. However, these signals may
still affect device operation. Table 4-3 lists all of the MC92610’s asynchronous
configuration and control signals and describes the effect of changing their state after power
up.
Table 4-3. Asynchronous Configuration and Control Signals
Signal Name
Description
Effect of Changed State
XCVR_x_RSEL
Transceiver Redundant Link Select
Receiver must acquire new bit phase
alignment; byte and word synchronization
must be re-established.
XCVR_x_DISABLE
Transceiver Disable
Receiver must acquire new bit phase
alignment; byte and word synchronization
must be re-established.
DROP_SYNC
Drop Synchronization
Receiver must re-establish byte and word
synchronization.
XMIT_REF_A
Transmitter Reference Clock A Select
Device must be reset.
RECV_REF_A
Receiver Reference Clock A Select
Device must be reset.
XMIT_EQ_EN
Transmitter Equalization Enable
May cause short burst of bit errors.
RECV_EQ_EN
Receiver Equalization Enable
May cause short burst of bit errors.
XMIT_EN_ALL
Transmitter Enable, All Outputs
No action required.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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