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參數(shù)資料
| 型號： | MC92610VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封裝： | 19 X 19 MM, 1.76 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAG-1, MAPBGA-324 |
| 文件頁數(shù)： | 24/104頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | MC92610VF |
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2-6
MC92610 SERDES User’s Manual
MOTOROLA
Functional Description
2.3.1.2
Transmitting Pre-Coded Data
Ten-bit pre-coded data may be transmitted, bypassing the internal 8B/10B encoder. Ten-Bit
Interface (TBI) mode is enabled by asserting TBIE high. In this mode, the ten bits to
transmit are presented on the XMIT_x_7–XMIT_x_0 inputs, and bits 8 and 9 on the
XMIT_x_K and XMIT_x_IDLE inputs, respectively.
Precautions must be taken when using TBI mode. The 10-bit pre-coded data must exhibit
the same properties as 8B/10B coded data. DC balance must be maintained and there must
be sufficient transition density to ensure reliable data recovery at the receiver.
The receiver requires that the K28.5 Idle character be periodically transmitted to enable
byte and word synchronization. This 10-bit pattern, ‘0011111010’ or ‘1100000101’
(ordered from bit 0 through 9) is used for alignment and link-to-link synchronization when
operating in any of the byte or word synchronization modes. The pattern of Idles and data
required to achieve byte or word synchronization depends on the configuration of the
receiver, see Section 3.3.4.3. The appropriate sequence must be applied through the
Ten-Bit Interface.
The MC92610 transmitter is comprised of several components whose operations are
described in the following sections.
2.3.1.3
Link Multiplexer Mode
Link multiplexer mode configures the MC92610 quad device into a dual transceiver. The
transmit data interfaces for transmitters A and B are combined to form a 16-bit/20-bit,
Single Data Rate (SDR) interface. The data is sampled and stored on the rising edge of the
transmit interface clock XMIT_A_CLK. The transmit data is aggregated and transmit out
of link A. The outputs of link B are disabled. The transmit interface may also be operated
in DDR mode by asserting DDRE high.
Likewise, transmit data interfaces C and D are combined and transmit out of link C.
Transmit interface clock XMIT_C_CLK is used for transmitters C and D. The outputs of
link D are disabled.
Table 2-2. Transmitter Control States
XMIT_x_IDLE
XMIT_x_K
Description
—
Low
Transmit data present on XMIT_x_7–XMIT_x_0
inputs.
Low
High
Transmit Idle (K28.5), ignore XMIT_x_7–XMIT_x_0
inputs.
High
Transmit control present on XMIT_x_7–XMIT_x_0
inputs.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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