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參數資料
| 型號： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數： | 10/60頁 |
| 文件大?。?/td> | 1296K |
| 代理商： | MPC7450RX667LX |
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18
MPC7450 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
Table 9. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
533 MHz
600 MHz
667 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
fcore
500
533
500
600
500
667
MHz
1
VCO frequency
fVCO
1000
1066
1000
1200
1000
1333
MHz
1
SYSCLK frequency
fSYSCLK
33
133
33
133
33
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5307.5
30
7.530
ns
SYSCLK rise and fall time
tKR and tKF
—1.0
ns
2
SYSCLK duty cycle
measured at OVDD/2
tKHKL/tSYSCLK
40
60
40
60
40
60
%
3
SYSCLK jitter
—
±150
—
±150
—
±150
ps
4, 6
Internal PLL relock time
—
100
—
100
—
100
s5
Notes:
1. Caution: The SYSCLK frequency, PLL_EXT and PLL_CFG[0:3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_EXT, PLL_CFG[0:3] signal description in
Section 1.9.1, “PLL Configuration,” for valid PLL_EXT and PLL_CFG[0:3] settings.
2. Rise and fall times for the SYSCLK input measured from 0.4 V to 1.4 V.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short term and long term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on reset sequence.
6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
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