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參數(shù)資料
| 型號(hào)： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 43/60頁 |
| 文件大小： | 1296K |
| 代理商： | MPC7450RX667LX |
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48
MPC7450 RISC Microprocessor Hardware Specifications
System Design Information
1.9.2 PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7450 to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in
Figure 22 using surface mount capacitors with minimum effective series inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery
of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint, without the
inductance of vias.
Figure 22. PLL Power Supply Filter Circuit
1.9.3 Power Supply Voltage Sequencing
The notes in Table 2 contain cautions about the sequencing of the external bus voltages and core voltage of
the MPC7450 (when they are different). These cautions are necessary for the long-term reliability of the
Table 19. Sample Core-to-L3 Frequencies
Core Frequency (MHz)
÷2
÷2.5
÷3
÷3.5
÷4
÷5
÷6
400
200
160
133
114
100
80
66
433
217
173
144
124
108
87
72
450
225
180
150
129
113
90
75
466
233
186
155
133
117
93
78
500
250
200
167
143
125
100
83
533
266
213
178
152
133
107
89
550
275
220
183
157
138
110
92
600
300
240
200
171
150
120
100
650
325
260
217
186
163
130
108
666
333
266
222
190
167
133
111
700
350
280
233
200
175
140
117
750
375
300
250
214
188
150
125
Note:
1. The core and L3 frequencies are for reference only. Some examples may represent core or L3 frequencies which
are not useful, not supported, or not tested for by the MPC7450; see Section 1.5.2.3, “L3 Clock AC
Specifications,” for valid L3_CLK frequencies. (Shaded cells do not comply with Table 9 of Section 1.5.2.1, “Clock
VDD
AVDD
10
2.2 F
GND
Low ESL Surface Mount Capacitors
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