參數(shù)資料
型號(hào)： MPC7450RX667LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483
封裝： 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483
文件頁數(shù)： 45/60頁
文件大小： 1296K
代理商： MPC7450RX667LX
MPC7450 RISC Microprocessor Hardware Specifications
5
Features
— 4-entry AltiVec issue queue can issue up to two instructions to two of the four AltiVec subunits
(simple, complex, permute, and floating-point).
— 16 AltiVec rename registers
— 2-entry floating point issue queue can issue one instruction to the floating point unit
— 16 FPR rename registers
Completion
— 16-entry completion buffer
— Instruction tracking and peak completion of three instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization, and all instruction flow changes
Simple fixed point units
— Three simple fixed point units (SFX0, SFX1, SFX2)
— Executes shift, rotate, compare, single-cycle arithmetics, logicals, count leading zeros, and
sign-extended arithmetics.
— Integer shift right and all shift/rotate/sign extend instructions with the record option require 2
cycles non-pipelined in the SFX. Their GPR results are returned with a latency of 1 cycle. Their
CR results and carry bit are returned with a latency of 2 cycles. Traps require 2 cycles to
execute.
— All other SFX instructions are single-cycle
Complex fixed point unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
— Executes multicycle fixed point instructions: multiply, divide
— Early out multiply
Floating-point unit
— Support for IEEE-754 standard single and double precision floating-point arithmetic
— 5-cycle latency, 1-cycle throughput, single or double precision multiply-add
— Hardware divide
— Hardware support for denormalized numbers
— Table lookup for reciprocal square root estimate instruction
— Early out divide iteration for reciprocal estimate instruction
— Time-deterministic non-IEEE mode
AltiVec unit
— 1-cycle latency simple AltiVec subunit
— 4-cycle latency complex AltiVec subunit
— 2-cycle latency permute AltiVec subunit
— 2- to 4-cycle latency floating-point AltiVec subunit
— All four AltiVec subunits fully pipelined
Load/store unit
— 3-cycle integer/vector load latency with 1-cycle throughput
— 4-cycle floating-point load latency with 1-cycle throughput
— Effective address generation
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