參數(shù)資料
型號: MPC7450RX667LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483
封裝: 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483
文件頁數(shù): 26/60頁
文件大?。?/td> 1296K
代理商: MPC7450RX667LX
32
MPC7450 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
1.5.2.5 IEEE 1149.1 AC Timing Specifications
Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14, Figure 15,
Table 15. JTAG AC Timing Specifications (Independent of SYSCLK)1
At recommended operating conditions. See Table 4.
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
fTCLK
033.3
MHz
TCK cycle time
t TCLK
30
—ns
TCK clock pulse width measured at 1.4 V
tJHJL
15
ns
TCK rise and fall times
tJR and tJF
02
ns
TRST assert time
tTRST
25
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
tDVJH
tIVJH
4
0
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
20
25
ns
3
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
20
25
ns
4
Output hold times:
Boundary-scan data
TDO
tJLDX
tJLOX
TBD
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
19
9
ns
4, 5
5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
load
(see Figure 13). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
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