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參數(shù)資料
| 型號： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 1296K |
| 代理商： | MPC7450RX667LX |
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26
MPC7450 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Inputs to the MPC7450 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs.
These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7450. An internal circuit delays
the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal
receiving latches. This delayed clock is used to capture the data into these latches which comprise the
receive FIFO. This clock is asynchronous to all other processor clocks. This latched data is subsequently
read out of the FIFO synchronously to the processor clock. The time between writing and reading the data
is set by the using the sample point settings defined in the L3CR register.
Table 13 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9,
Table 13. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See Table 4.
Parameter
Symbol
533, 600, 667 MHz
Unit
Notes
Min
Max
L3_CLK rise and fall time
tL3CR and tL3CF
—1.0
ns
1
Setup times:
Data and parity
tL3DVEH and tL3DVEL
–(tL3_ECHO_CLK/4
– 0.35)
—ns
2, 3, 4
Input hold times:Data and parity
tL3DXEH and tL3DXEL
tL3_ECHO_CLK/4
+ 0.35
—ns
2, 4
Valid times:
Data and parity
All other outputs
tL3CHDV and tL3CLDV
tL3CHOV
—
–tL3_CLK/4 + 0.5
tL3_CLK/4 + 1.0
ns
5, 6, 7
5, 7
Output hold times:
Data and parity
All other outputs
tL3CHDX and tL3CLDX
tL3CHOX
tL3_CLK/4 – 0.35
tL3_CLK/4 + 0.5
—
ns
5, 6, 7
5, 7
L3_CLK to high impedance:
Data and parity
All other outputs
tL3CLDZ
tL3CHOZ
—
tL3_CLK/2
tL3_CLK/4 + 2.0
ns
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV DD.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint
voltage of the rising or falling edge of the input L3_ECHO_CLK
n (see Figure 10). Input timings are measured at
the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLK
n as shown in Figure 10. For consistency
with other input setup time specifications, this will be treated as negative input setup time.
4. tL3_ECHO_CLK/4 is one-fourth the period of L3_ECHO_CLKn. This parameter indicates that the MPC7450 can
latch an input signal that is valid for only a short time before and a short time after the midpoint between the
rising and falling (or falling and rising) edges of L3_ECHO_CLK
n at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the
falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins.
All output timings assume a purely resistive 50-
load (see Figure 8).
6. For DDR, the output data will typically lead the edge of L3_CLK
n as shown in Figure 10. For consistency with
other output valid time specifications, this will be treated as negative output valid time.
7. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is
actually launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to
the output valid and output hold times such that the specified output signal will be valid for approximately one
L3_CLK period starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending
one-fourth of a clock period after the edge it will be sampled.
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