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參數(shù)資料
| 型號(hào)： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大小： | 1296K |
| 代理商： | MPC7450RX667LX |
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MPC7450 RISC Microprocessor Hardware Specifications
17
Electrical and Thermal Characteristics
Table 8 provides the power consumption for the MPC7450.
1.5.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7450. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_EXT and PLL_CFG[0:3] signals.
Parts are sold by maximum processor core frequency; see Section 1.11, “Ordering Information.”
1.5.2.1 Clock AC Specifications
Table 8. Power Consumption for MPC7450
Processor (CPU) Frequency
Unit
Notes
533 MHz
600 MHz
667 MHz
Full-On Mode
Typical
11.6
13.0
14.5
W
1, 3
Maximum
15.2
17.5
19.0
W
1, 2
Doze Mode
Typical
TBD
W
1, 3
Nap Mode
Typical
1.3
1.4
1.7
W
1, 3
Sleep Mode
Typical
0.6
0.7
0.8
W
1, 3
Sleep Mode—PLL Disabled
Typical
410
460
510
mW
1, 3
Maximum
TBD
W
1, 2
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power
(OVDD and GVDD) or PLL supply power (AVDD). OVDD, and GVDD power is system dependent, but is typically
<20% of VDD power. Worst case power consumption for AVDD < 3 mW.
2. Maximum power is measured at nominal VDD (see Table 4) while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, without or with AltiVec, maximally busy.
3. Typical power is an average value measured at the nominal recommended VDD (see Table 4) in a system while
running a typical code sequence.
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