參數(shù)資料
型號： MPC7450RX667LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483
封裝： 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483
文件頁數(shù)： 34/60頁
文件大小： 1296K
代理商： MPC7450RX667LX
4
MPC7450 RISC Microprocessor Hardware Specifications
Features
1.2 Features
This section summarizes features of the MPC7450 implementation of the PowerPC architecture. Major
features of the MPC7450 are as follows:
7-stage pipeline control
— Fetch 1
— Fetch 2
—Dispatch
— Issue
—Execute
— Complete
— Writeback
Fetch and branch processing unit
— Four instructions fetched per clock
— 12-entry instruction buffer
— Branch folding
— One branch processed per cycle (plus resolving two speculations)
— Up to three outstanding, unresolved branches.
— 2048-entry branch history table (BHT) for dynamic prediction
— 128-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch
delay slots. Each entry caches up to four instructions.
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch three instructions to the issue queues. Up to three instructions can go to general
purpose (GP) issue queue in a cycle. Up to two instructions can go to AltiVec issue queue in a
cycle. One instruction can go to floating point (FPR) issue queue in a cycle. All load/store unit
instructions go to GP issue queue.
— Serialization control (combinations of the following):
– execution serialization—The instruction is dispatched and waits in the reservation station of
the execution unit until it is ready to be completed. An “execute_sync” is signaled by the
completion buffer, the instruction executes, and is completed.
– refetch serialization—The instruction causes all subsequent instructions to be flushed and
refetched. Two examples are the “isync” instruction and integer arithmetic overflow when
it sets the SO bit.
– store serialization—The instruction can only be completed when it is the oldest instruction
in the machine.
— Multiple and string fracturing (lmw, stmw, lswi, lswx, stswi, stswx). Multiples are converted
into independent load or store word immediate instructions and dispatched to the general
purpose register issue queue. String instructions are similarly fractured.
Separate instruction issue queues for each register file
— 6-entry GP issue queue can issue three instructions to any of three fixed point units, load/store
unit, and complex fixed point unit.
— 16 GPR rename registers
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