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參數(shù)資料
| 型號： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 56/60頁 |
| 文件大?。?/td> | 1296K |
| 代理商： | MPC7450RX667LX |
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MPC7450 RISC Microprocessor Hardware Specifications
Features
— Hits under misses (multiple outstanding misses)
— Single-cycle unaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Executes the cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian supported
— Supports FXU, FPU, and AltiVec load/store traffic
— Complete support for all four architecture AltiVec DST streams
Level 1 cache structure
— 32-Kbyte, 32-byte line, 8-way set associative instruction cache
— 32-Kbyte, 32-byte line, 8-way set associative data cache
— Byte parity on data cache, word parity on instruction cache
— 2-cycle cache access
— Pseudo LRU replacement (binary tree)
— Copyback or write-through data cache (on a page-per-page basis)
— Supports all PowerPC memory coherency modes
— Non-blocking data cache
— Cache locking supported for any combinations of ways in both instruction and data caches
Level 2 cache
— On-chip 256K 8-way set associative L2 cache
— 64-byte, 2-sectored line size
— Fully pipelined L2 cache access (single-cycle throughput)
— Total of 9 cycle load latency for L1 miss which hits in L2
— Copyback or write-through data cache (on a page basis)
— Storage of data, instructions, or both, in the cache
— Parity supported on cache and tags
— Pseudorandom replacement
Level 3 cache interface
— Internal L3 cache controller and tags; external data SRAMs
— 1- and 2-Mbyte, 8-way set associative L3 cache support
— 64-byte, 2-sectored line size for 1-Mbyte configuration
— 128-byte, 4-sectored line size for 2-Mbyte configuration
— Copyback or write-through data cache (on a page basis)
— Storage of data, instructions, or both, in the cache
— Parity support on cache and tags
— Pseudorandom replacement
— MSUG2 DDR SRAMs, Late Write SRAMs, and PB2 SRAMs supported
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| MPC745BPX300LE | 功能描述:微處理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC745BPX350LE | 功能描述:微處理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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