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參數(shù)資料
| 型號(hào)： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 16/60頁 |
| 文件大?。?/td> | 1296K |
| 代理商： | MPC7450RX667LX |
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MPC7450 RISC Microprocessor Hardware Specifications
23
Electrical and Thermal Characteristics
1.5.2.3 L3 Clock AC Specifications
The L3_CLK frequency is programmed by the L3 configuration register (L3CR[6:8]) core-to-L3 divisor
ratio. See Table 19 for example core and L3 frequencies at various divisors. Table 11 provides the potential
range of L3_CLK output AC timing specifications as defined in Figure 7.
The maximum L3_CLK frequency shown in Table 11 is the core frequency divided by two. Very few L3
SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L3 divisor to
provide a longer L3_CLK period for read and write access to the L3 SRAMs. The maximum L3_CLK
frequency for any application of the MPC7450 will be a function of the AC timings of the MPC7450, the
AC timings for the SRAM, bus loading, and printed circuit board trace length.
Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a
socketed part on a functional tester at the maximum frequencies of Table 11. Therefore, functional operation
and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 200 MHz or
less.
Notes:
1. The maximum L3 clock frequency will be system dependent. See Section 1.5.2.3, “L3 Clock AC Specifications” for
an explanation that this maximum frequency is not functionally tested at speed by Motorola.
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control
signals which are common to both SRAM chips in the L3.
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for
PB2 or Late Write SRAM. This parameter is critical to the write data signals which are separately latched onto each
SRAM part by these pairs of signals.
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address/data/
control signals equally and, therefore, is already comprehended in the AC timing and does not have to be
considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period
caused by supply voltage noise or thermal effects. This must be accounted for, along with clock skew, in any L3
timing analysis.
Table 11. L3_CLK Output AC Timing Specifications
At recommended operating conditions. See Table 4.
Parameter
Symbol
533 MHz
600 MHz
667 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
L3 clock frequency
fL3_CLK
75
266
75
266
75
266
MHz
1
L3 clock cycle time
tL3_CLK
3.75
13.3
3.76
13.3
3.75
13.3
ns
L3 clock duty cycle
tCHCL/tL3_CLK
50
%
2
L3 clock output-to-output
skew (L1_CLK0 to
L1_CLK1)
tL3CSKW1
—
200
—
200
—
200
ps
3
L3 clock output-to-output
skew (L1_CLK[0:1] to
L1_ECHO_CLK[1:3])
tL3CSKW2
—
100
—
100
—
100
ps
4
L3 clock jitter
—
±50
—
±50
—
±50
ps
5
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