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參數(shù)資料
| 型號： | MPC7450RX667LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483 |
| 封裝： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件頁數(shù)： | 22/60頁 |
| 文件大?。?/td> | 1296K |
| 代理商： | MPC7450RX667LX |
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MPC7450 RISC Microprocessor Hardware Specifications
29
Electrical and Thermal Characteristics
1.5.2.4.2 L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or Late Write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11. These SRAMs are synchronous to the MPC7450; one L3_CLKn signal is output to each SRAM
to latch address, control, and write data. Read data is launched by the SRAM synchronous to the delayed
L3_CLKn signal it received. The MPC7450 needs a copy of that delayed clock which launched the SRAM
read data to know when the returning data will be valid. Therefore, L3_ECHO_CLK1 and
L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the MPC7450 inputs
L3_ECHO_CLK0 and L3_ECHO_CLK2 respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are
phase-aligned with the input clock received at the SRAMs. The MPC7450 will latch the incoming data on
the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
Table 14 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11,
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter
Symbol
533, 600, 667 MHz
Unit
Notes
Min
Max
L3_CLK rise and fall time
tL3CR and tL3CF
—
1.0
ns
1, 5
Setup times:
Data and parity
t
1.5
—
ns
2, 5
Input hold times:
Data and parity
tL3DXEH
—
0.5
ns
2, 5
Valid times:
Data and parity
All other outputs
tL3CHDV
tL3CHOV
—
tL3_CLK/4 + 1.0
ns
3, 4, 5
4
Output hold times:
Data and parity
All other outputs
tL3CHDX
tL3CHOX
tL3_CLK/4 + 0.5
—
ns
3, 4, 5
4, 5
L3_CLK to high impedance: Data and parity
All other outputs
tL3CHDZ
tL3CHOZ
—
2.0
ns
5
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV DD.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the
rising edge of the input L3_ECHO_CLK
n (see Figure 10). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLK
n to the midpoint of
the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-
load (see Figure 10).
4. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output
valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a
clock period after the edge it will be sampled.
5. Timing behavior and characterization are currently being evaluated.
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