參數(shù)資料
型號(hào)： MPC7450RX667LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483
封裝： 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483
文件頁(yè)數(shù)： 46/60頁(yè)
文件大小： 1296K
代理商： MPC7450RX667LX
50
MPC7450 RISC Microprocessor Hardware Specifications
System Design Information
1.9.6 Output Buffer DC Impedance
The MPC7450 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature.
To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of
each resistor is varied until the pad voltage is OVDD/2 (see Figure 24).
The output impedance is the average of two components, the resistances of the pull-up and pull-down
devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the
pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1
is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes
the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 =
(RP + RN)/2.
Figure 24. Driver Impedance Measurement
Table 20 summarizes the signal impedance results. The impedance increases with junction temperature and
is relatively unaffected by bus voltage.
1.9.7 Pull-Up/Pull-Down Resistor Requirements
The MPC7450 requires high-resistive (weak: 4.7 k
) pull-up resistors on several control pins of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the MPC7450 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper
device operation. For the MPC7440, 360 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE
and TEST[0:3]; the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the
Table 20. Impedance Characteristics
VDD = 1.5 V, OVDD = 1.8 V ± 5%, Tj = 5°–85°C
Impedance
Processor Bus
L3 Bus
Unit
Z0
Typical
33–42
34–42
Maximum
31–51
32–44
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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