參數(shù)資料
型號(hào)： MPC7450RX667LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 667 MHz, RISC PROCESSOR, CBGA483
封裝： 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483
文件頁(yè)數(shù)： 58/60頁(yè)
文件大?。?/td> 1296K
代理商： MPC7450RX667LX
MPC7450 RISC Microprocessor Hardware Specifications
7
Features
— Support for direct mapped memory
— 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, and 6:1 core-to-L3 frequency ratios supported
— Selectable interface voltages of 1.5 V, 1.8 V, and 2.5 V
Memory management unit
— 128-entry, 2-way set associative instruction TLB
— 128-entry, 2-way set associative data TLB
— Both hardware and software reloads for TLBs are available
— Four instruction BATs and four data BATs
— Virtual memory support for up to 4 exabytes (2
52) of virtual memory
— Real memory support for up to 64 gigabytes (236) of physical memory
Efficient data flow
— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide
— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF
— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
— Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus
— Up to seven outstanding, out-of-order transactions on the bus
— Load folding to fold new dL1 misses into older, outstanding load, and store misses to the same
line
— Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e.,
address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).
— 2-entry finished store queue and 4-entry completed store queue between load/store unit and dL1
— Separate additional queues for efficient buffering of outbound data (castouts, write-throughs,
etc.) from dL1 and L2
Bus interface
— MPX bus processor interface
— Subset of 60x bus supported
— 36-bit physical address bus
— 64-bit data bus
— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,
8x, 9x, 10x, 11x, 12x, 13x, 14x, 15x, and 16x supported
— Selectable interface voltages of 1.8 V and 2.5 V
Power management
— Low-power design with thermal requirements very similar to MPC7400 and MPC750
— 1.6-V processor core (1.8-V processor core still supported)
— Selectable interface voltages can reduce power in output buffers
— Three static power saving modes: doze, nap, and sleep
— Dynamic power management
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
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