參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 13/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
1-12
Memory Controller Signals
1.5 Memory Controller Signals
Refer to the Memory Controller chapter in the MSC8102 Reference Manual for detailed information
about configuring these signals.
Table 1-6. Memory Controller Signals
Signal Name
Type
Description
BCTL0
Output
System Bus Buffer Control 0
Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin
is defined by the value of SIUMCR[BCTLC].
BCTL1
CS5
Output
System Bus Buffer Control 1
Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin
is defined by the value of SIUMCR[BCTLC].
System and Local Bus Chip Select 5
Enables specific memory devices or peripherals connected to MSC8102 buses.
BM[0–2]
TC[0–2]
BNKSEL[0–2]
Input
Input/
Output
Boot Mode 0–2
Defines the boot mode of the MSC8102. This signal is sampled on PORESET deassertion.
Transfer Code 0–2
The bus master drives these pins during the address tenure to specify the type of the
code.
Bank Select 0–2
Selects the SDRAM bank when the MSC8102 is in 60x-compatible bus mode.
ALE
Output
Address Latch Enable
Controls the external address latch used in an external master bus.
PWE[0–3]
PSDDQM[0–3]
PBS[0–3]
Output
System Bus Write Enable
Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte
lanes for write operations.
System Bus SDRAM DQM
From the SDRAM control machine. These pins select specific byte lanes of SDRAM
devices.
System Bus UPM Byte Select
From the UPM in the memory controller, these signals select specific byte lanes during
memory operations. The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port size of the
accessed device.
PSDA10
PGPL0
Output
System Bus SDRAM A10
From the bus SDRAM controller. The precharge command defines which bank is
precharged. When the row address is driven, it is a part of the row address. When column
address is driven, it is a part of column address.
System Bus UPM General-Purpose Line 0
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
PSDWE
PGPL1
Output
System Bus SDRAM Write Enable
From the bus SDRAM controller. Should connect to SDRAM WE input.
System Bus UPM General-Purpose Line 1
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
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