參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 93/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
4-5
Layout Practices
4.5 Layout Practices
Each VCC and VDD pin on the MSC8102 should be provided with a low-impedance path to the board
power supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The
power supply pins drive distinct groups of logic on the chip. The VCC power supply should be bypassed
to ground using at least four 0.1 F by-pass capacitors located as closely as possible to the four sides of
the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and
GND
should be kept to less than half an inch per capacitor lead. A four-layer board is recommended,
employing two inner layers as VCC and GND planes.
All output pins on the MSC8102 have fast rise and fall times. PCB trace interconnection length should be
minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of
six inches are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during
reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
There is one pair of PLL supply pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power
to the VCCSYN input with a circuit similar to the one in Figure 4-3. To filter as much noise as possible,
place the circuit as close as possible to VCCSYN. The 0.01-F capacitor should be closest to VCCSYN,
followed by the 10-F capacitor, the 10-nH inductor, and finally the 10-
resistor to V
DD. These traces
should be kept short and direct.
GNDSYN should be provided with an extremely low impedance path to ground and should be bypassed to
VCCSYN by a 0.01-F capacitor located as close as possible to the chip package. The user should also
bypass GNDSYN to VCCSYN with a 0.01-F capacitor as close as possible to the chip package
Figure 4-3. VCCSYN Bypass
VDD
0.01 F
10 F
VCCSYN
10
10nH
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