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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 3/96頁 |
| 文件大小： | 1557K |
| 代理商： | MSC8102M4000 |
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1-3
Power Signals
1.1 Power Signals
1.2 Clock Signals
Table 1-2. Power and Ground Signal Inputs
Signal Name
Description
VDD
Internal Logic Power
VDD dedicated for use with the device core. The voltage should be well-regulated and the input
should be provided with an extremely low impedance path to the VDD power rail.
VDDH
Input/Output Power
This source supplies power for the I/O buffers. The user must provide adequate external decoupling
capacitors.
VCCSYN
System PLL Power
VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated
and the input should be provided with an extremely low impedance path to the VCC power rail.
GND
System Ground
An isolated ground for the internal processing logic and I/O buffers. This connection must be tied
externally to all chip ground connections, except GNDSYN. The user must provide adequate external
decoupling capacitors.
GNDSYN
System PLL Ground
Ground dedicated for system PLL use. The connection should be provided with an extremely
low-impedance path to ground.
Table 1-3. Clock Signals
Signal Name
Type
Signal Description
CLKIN
Input
Clock In
Primary clock input to the MSC8102 PLL.
CLKOUT
Output
Clock Out
The bus clock.
DLLIN
Input
DLLIN
Synchronizes the internal clocks with an external device.
Note:
When the DLL is disabled, pull this pin low (GND).
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