參數(shù)資料
型號： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁數(shù)： 67/96頁
文件大小： 1557K
代理商： MSC8102M4000
vii
— Single-wire and loop operations.
Timers
— Two modules of 16 timers each.
— Each timer has the following features:
°
Cyclic or one-shot.
°
Input clock polarity control.
°
Interrupt request when counting reaches a programmed threshold.
°
Pulse or level interrupts.
°
Dynamically updated programmed threshold.
°
Read counter any time.
— Watchdog mode for the timers that connect to the device.
Hardware semaphores. Eight coded hardware semaphores, locked by simple write access without need
for read-modify-write mechanism.
General-Purpose I/O (GPIO) port:
— 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.
— Each port can be programmed separately to serve up to two dedicated peripherals, and each port
supports open-drain output mode.
Global Interrupt Controller (GIC):
— Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to
INT_OUT, NMI_OUT, and to the cores.
— Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.
— Generation of virtual NMI (one to each SC140 core) by a simple write access.
Software support, with support from industry-leading third parties:
— Real-Time Operating Systems (RTOS):
°
Fully supports MSC8102 device architecture (multi-core, memory hierarchy, ICache, timers,
DMA, interrupts, peripherals).
–
High-performance and deterministic, delivering predictive response time.
–
Optimized to provide low interrupt latency with high data throughput.
–
Preemptive and priority-based multitasking.
–
Fully interrupt/event driven.
–
Small memory footprint.
–
Comprehensive set of APIs.
–
Fully supports MSC8102 DMA, interrupts, and timer schemes.
°
Multi-core support:
–
Enables use of one instance of kernel code all four SC140 cores.
–
Dynamic and static memory allocation from local memory (M1) and shared memory
(M2).
°
Distributed system support, enables transparent inter-task communications between tasks
running inside the SC140 cores and the other tasks running on devices on the board or remote
devices in the network
–
Messaging mechanism between tasks using mailboxes and semaphores.
–
Networking support; data transfer between tasks running inside and outside the device
using networking protocols.
–
Includes integrated device drivers for such peripherals as TDM, UART, and external
buses.
°
Additional features:
–
Incorporates task debugging utilities integrated with compilers and vendors.
–
Board support package (BSP) for MSC8102ADS.
— Integrated Development Environment (IDE):
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