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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 4/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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1-4
Reset and Configuration Signals
1.3 Reset and Configuration Signals
1.4 Direct Slave Interface, System Bus, and Interrupt
Signals
The direct slave interface (DSI) is combined with the system bus because they share some common
signal lines. Individual assignment of a signal to a specific signal line is configured through internal
registers. Table 1-5 describes the signals in this group.
Note:
Although there are fifteen interrupt request (IRQ) connections to the core processors, there are
multiple external lines that can connect to these internal signal lines. After reset, the default
configuration enables only IRQ[1–7], but includes two input lines each for IRQ[1–3] and
IRQ7. The designer must select one line for each required interrupt and reconfigure the other
external signal line or lines for alternate functions. Additional alternate IRQ lines and
IRQ[8–15] are enabled through the GPIO signal lines.
Table 1-4. Reset and Configuration Signals
Signal Name
Type
Signal Description
PORESET
Input
Power-On Reset
When asserted, this line causes the MSC8102 to enter power-on reset state.
RSTCONF
Input
Reset Configuration
1
Used during reset configuration sequence of the chip. A detailed explanation of its function
is provided in the MSC8102 Reference Manual. This signal is sampled upon deassertion
of PORESET.
HRESET
Input
Hard Reset
When asserted, this open-drain line causes the MSC8102 to enter hard reset state.
SRESET
Input
Soft Reset
When asserted, this open-drain line causes the MSC8102 to enter soft reset state.
Note:
When PORESET is deasserted, the MSC8102 also samples the following signals:
BM[0–2]—Selects the boot mode.
MODCK[1–2]—Selects the clock configuration.
SWTE—Enables the software watchdog timer.
DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.
Refer to Table 1-5 for details on these signals.
Table 1-5. DSI, System Bus, and Interrupt Signals
Signal Name
Type
Description
HD0
SWTE
Input/
Output
Input
Host Data Bus 0
Bit 0 of the DSI data bus.
Software Watchdog Timer Disable.
It is sampled on the rising edge of PORESET signal.
HD1
DSISYNC
Input/
Output
Input
Host Data Bus 1
Bit 1 of the DSI data bus.
DSI Synchronous
Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled
on the rising edge of PORESET signal.
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