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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 56/96頁 |
| 文件大小： | 1557K |
| 代理商： | MSC8102M4000 |
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— Hardware A-law/
-law conversion
— Up to 50 Mbps per TDM (50 MHz bit clock if one data line is used, 25 MHz if two data lines are
used, 12.5 MHz if four data lines are used).
— Up to 256 channels.
— Up to 16 MB per channel buffer (granularity 8 bytes), where A/
law buffer size is double
(granularity 16 byte)
— Receive buffers share one global write offset pointer that is written to the same offset relative to
their start address.
— Transmit buffers share one global read offset pointer that is read from the same offset relative to
their start address.
— All channels share the same word size.
— Two programmable receive and two programmable transmit threshold levels with interrupt
generation that can be used, for example, to implement double buffering.
— Each channel can be programmed to be active or inactive.
— 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels,
respectively.
— The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.
— Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the
falling edge of the clock.
— Frame sync can be programmed as active low or active high.
— Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.
— MSB or LSB first support.
UART
— Two signals for transmit data and receive data.
— No clock, asynchronous mode.
— Can be serviced either by the SC140 DSP cores or an external host on the 60x-compatible system
bus or on the DSI.
— Full-duplex operation.
— Standard mark/space non-return-to-zero (NRZ) format.
— 13-bit baud rate selection.
— Programmable 8-bit or 9-bit data format.
— Separately enabled transmitter and receiver.
— Programmable transmitter output polarity.
— Two receiver wakeup methods:
°
Idle line wakeup.
°
Address mark wakeup.
— Separate receiver and transmitter interrupt requests.
— Eight flags, the first five can generate interrupt request:
°
Transmitter empty.
°
Transmission complete.
°
Receiver full.
°
Idle receiver input.
°
Receiver overrun.
°
Noise error.
°
Framing error.
°
Parity error.
— Receiver framing error detection.
— Hardware parity checking.
— 1/16 bit-time noise detection.
— Maximum bit rate 6.25 Mbps.
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相關代理商/技術(shù)參數(shù) |
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|---|---|
| MSC8102M4400 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
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| MSC8102UG | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor |
| MSC8103 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MSC8103/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
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