參數(shù)資料
型號： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁數(shù)： 6/96頁
文件大?。?/td> 1557K
代理商： MSC8102M4000
1-6
Direct Slave Interface, System Bus, and Interrupt Signals
HWBS[4–7]
HDBS[4–7]
HWBE[4–7]
HDBE[4–7]
PWE[4–7]
PSDDQM[4–7]
PBS[4–7]
Input
Output
Host Write Byte Strobes (In Asynchronous dual mode)
One bit per byte is used as a strobe for host write accesses.
Host Data Byte Strobe (in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
Host Write Byte Enable (In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host write accesses.
Host Data Byte Enable (in Synchronous single mode)
One bit per byte is used as a strobe enable for host read or write accesses
System Bus Write Enable
Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte
lanes for write operations.
System Bus SDRAM DQM
From the SDRAM control machine. These pins select specific byte lanes of SDRAM
devices.
System Bus UPM Byte Select
From the UPM in the memory controller, these signals select specific byte lanes during
memory operations. The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port size of the
accessed device.
HRDS
HRW
HRDE
Input
Host Read Data Strobe (In Asynchronous dual mode)
Used as a strobe for host read accesses.
Host Read/Write Select (in Asynchronous/Synchronous single mode)
Host read/write select.
Host Read Data Enable (In Synchronous dual mode)
Indicates valid data for host read accesses.
HBRST
Input
Host Burst
The host asserts this pin to indicate that the current transaction is a burst transaction in
synchronous mode only.
HDST0
Input
Host Data structure 0
Defines the data structure of the host access in DSI little-endian mode.
HDST1
Input
Host Data structure 1
Defines the data structure of the host access in DSI little-endian mode.
HCS
Input
Host Chip Select
DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the
Chip_ID.
HBCS
Input
Host Broadcast Chip Select
DSI chip select for broadcast mode. Enables more than one DSI to share the same host
chip-select pin for broadcast write accesses.
HTA
Output
Host Transfer Acknowledge
Upon a read access, indicates to the host when the data on the data bus is valid. Upon a
write access, indicates to the host that the data on the data bus was written to the DSI
write buffer.
HCLKIN
Input
Host Clock Input
Host clock signal for DSI synchronous mode.
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
Type
Description
相關(guān)PDF資料
PDF描述
MSC8122TVT6400 32-BIT, 400 MHz, OTHER DSP, PBGA431
MSC8122TVT4800V 32-BIT, 300 MHz, OTHER DSP, PBGA431
MSC8122MP8000 32-BIT, 500 MHz, OTHER DSP, PBGA431
MSC8144ETVT800B 133 MHz, OTHER DSP, PBGA783
MSC8144EVT1000A 133 MHz, OTHER DSP, PBGA783
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8102M4400 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8102RM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8102UG 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8103 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor
MSC8103/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*