參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 5/96頁(yè)
文件大小： 1557K
代理商： MSC8102M4000
1-5
Direct Slave Interface, System Bus, and Interrupt Signals
HD2
DSI64
Input/
Output
Input
Host Data Bus 2
Bit 2 of the DSI data bus.
DSI 64
Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of
PORESET signal.
HD3
MODCK1
Input/
Output
Input
Host Data Bus 3
Bit 3 of the DSI data bus.
Clock Mode 1
Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
HD4
MODCK2
Input/
Output
Input
Host Data Bus 4
Bit 4 of the DSI data bus.
Clock Mode 2
Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
HD5
CNFGS
Input/
Output
Input
Host Data Bus 5
Bit 5 of the DSI data bus.
Configuration Source
One signal out of two that indicates reset configuration mode. It is sampled on the rising
edge of PORESET signal.
HD[6–31]
Input/O
utput
Host Data Bus 6–31
Bits 6–31 of the DSI data bus.
HD[32–63]
D[32–63]
Input/O
utput
Input/O
utput
Host Data Bus 32–63
Bits 32–63 of the DSI data bus.
System Bus Data 32–63
In write transactions, the bus master drives the valid data on this bus. In read transactions,
the slave drives the valid data on this bus.
HCID[0–3]
Input
Host Chip ID 0–3
Carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]
matches the Chip_ID, or if HBCS is asserted.
HA[11–29]
Input
Host Bus Address 11–29
Used by external host to access the internal address space.
HWBS[0–3]
HDBS[0–3]
HWBE[0–3]
HDBE[0–3]
Input
Host Write Byte Strobes (In Asynchronous dual mode)
One bit per byte is used as a strobe for host write accesses.
Host Data Byte Strobe (in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
Host Write Byte Enable (In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host read or write accesses.
Host Data Byte Enable (in Synchronous single mode)
One bit per byte is used as a strobe enable for host write accesses
Table 1-5. DSI, System Bus, and Interrupt Signals (Continued)
Signal Name
Type
Description
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