參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 34/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
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Features
Four high-performance StarCore SC140 Digital Signal Processor (DSP) extended cores delivering up
to 4400 MMACS using 16 ALUs running at up to 275 MHz, delivering a performance equivalent to a
single SC140 core running at 1.1 GHz
Each extended core includes:
— SC140 core processor.
— Local 224 KB memory space (M1) accessed by the SC140 core with no wait states and atomic
access.
— 16 KB, 16-way instruction cache (ICache).
— Programmable interrupt controller (PIC).
— Local interrupt controller (LIC).
Each SC140 core provides the following:
— Up to 1100 million multiply-accumulates per second (MMACS) using an internal 275 MHz clock
at 1.6 V. A multiply-accumulate operation includes a multiply-add instruction with the associated
data move and pointer update.
— 4 ALUs per SC140 core.
— 16 data registers, 40 bits each.
— 27 address registers, 32 bits each.
— Hardware support for fractional and integer data types.
— Very rich 16-bit wide orthogonal instruction set.
— Up to six instructions executed in a single clock cycle.
— Variable-length execution set (VLES) that can be optimized for code density and performance.
— IEEE 1149.1 JTAG port.
— Enhanced on-device emulation (EOnCE) module with real-time debugging capabilities.
Large internal memory spaces (1.440 MB total).
— 224 KB of M1 memory per core (896 KB total).
— 16 KB of ICache per core (64 KB total).
— 476 KB shared memory (M2) operating at the core frequency, accessible from all four SC140
cores via the MQBus, and accessible from the local bus.
— 4 KB boot ROM accessible from all four SC140 cores via the MQBus.
Internal PLL for generating up to 275 MHz clock for the SC140 cores and up to 91.67 MHz for the
60x-compatible system bus, the local bus and other modules. PLL values are determined at reset based
on configuration signal values.
Very flexible System Interface Unit (SIU) with a memory controller to support a 32/64-bit wide
60x-compatible system bus to access memory and memory-mapped devices:
— Reset controller.
— Real-time clock register.
— Periodic interrupt timer (PIT).
— Hardware bus monitors for the 60x-compatible system bus and local bus.
— Software watchdog timer function.
Flexible eight-bank memory controller:
— Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a
page-mode SDRAM machine.
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, FLASH and other
user-definable peripherals.
— Byte enables for either 64-bit or 32-bit bus width mode.
— Eight external memory banks (banks 0–7). Two additional memory banks control IPBus
peripherals and internal memories (banks 9, 11). Each bank has the following features:
相關(guān)PDF資料
PDF描述
MSC8122TVT6400 32-BIT, 400 MHz, OTHER DSP, PBGA431
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MSC8144ETVT800B 133 MHz, OTHER DSP, PBGA783
MSC8144EVT1000A 133 MHz, OTHER DSP, PBGA783
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