參數(shù)資料
型號: MSC8102M4000
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝: 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁數(shù): 14/96頁
文件大?。?/td> 1557K
代理商: MSC8102M4000
1-13
Memory Controller Signals
POE
PSDRAS
PGPL2
Output
System Bus Output Enable
From the bus GPCM. Controls the output buffer of memory devices during read
operations.
System Bus SDRAM RAS
From the bus SDRAM controller. Should connect to SDRAM RAS input.
System Bus UPM General-Purpose Line 2
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
PSDCAS
PGPL3
Output
System Bus SDRAM CAS
From the bus SDRAM controller. Should connect to SDRAM CAS input.
System Bus UPM General-Purpose Line 3
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
PGTA
PUPMWAIT
PGPL4
PPBS
Input
Output
System GPCM TA
Terminates external transactions during GPCM operation. Requires an external pull-up
resistor for proper operation.
System Bus UPM Wait
An external device holds this pin low to force the UPM to wait until the device is ready to
continue the operation.
System Bus UPM General-Purpose Line 4
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
System Bus Parity Byte Select
In systems that store data parity in a separate chip, this output is used as the byte-select
for that chip.
PSDAMUX
PGPL5
Output
System Bus SDRAM Address Multiplexer
Controls the system bus SDRAM address multiplexer when the MSC8102 is in external
master mode.
System Bus UPM General-Purpose Line 5
One of six general-purpose output lines from the UPM. The values and timing of this pin
are programmed in the UPM.
Table 1-6. Memory Controller Signals (Continued)
Signal Name
Type
Description
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