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參數(shù)資料
| 型號： | MSC8102M4000 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CBGA431 |
| 封裝： | 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431 |
| 文件頁數(shù)： | 91/96頁 |
| 文件大?。?/td> | 1557K |
| 代理商： | MSC8102M4000 |
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4-3
Connectivity Guidelines
4.3 Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to their non-active
value, except for the following:
If the DSI is unused (bit DDR[1]:DSIDIS is set), then HCS and HBCS must be tied to VDD and all the
rest of the DSI signals can be disconnected.
When the DSI uses Synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be
pulled either up or down depending on design requirements.
HDST can be disconnected if the DSI is in Big-endian mode, or if the DSI is in Little-endian mode and
DCR[7]:DSRFA bit is set.
When the DSI is in 64-bit Data bus mode and DCR[2]:BEM is cleared, the
HWBS[1–3]
/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] and
HWBS[4–7]
/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7] must be tied to
VDD.
When the DSI is in 32-bit Data bus mode and DCR[2] (BEM) is cleared,
HWBS[1–3]
/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be tied to VDD.
When the DSI is in Asynchronous mode, HBRST and HCLKIN should either be disconnected or tied to
VDD.
The following signals can be disconnected in Single-master mode (BCR[EBM] is reset): BG, DBG,
EXT_BG[2–3]
, EXT_DBG[2-3], GBL and TS.
The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.
In Single master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active
value. In other modes, they must be pulled up.
Figure 4-2. Core Power Supply Decoupling
+
-
Power supply
or
Voltage Regulator
High Freq. capacitors
(very low ESR and ESL)
Bulk/Tantalum capacitors
with low ESR and ESL
MSC8102
maximum IR drop
of 15 mV at 1 A
Capacitors of 150
f
Lmax = 2 cm
One 0.01 mF capacitor
for every 3 Core supply
(Imin = 3 A)
pads.
1.6 V
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