參數(shù)資料
型號(hào): MSC8102M4000
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝: 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù): 51/96頁(yè)
文件大小: 1557K
代理商: MSC8102M4000
3-1
Chapter 3
Packaging
3.1 Pinout and Package Information
This sections provides information about the MSC8102 package, including diagrams of the package
pinouts and tables showing how the signals discussed in Chapter 1, Signal/Connection Descriptions are
allocated. The MSC8102 is available in a 431-pin High Temperature Coefficient for Expansion Flip
Chip-Ceramic Ball Grid Array (FC-CBGA (HCTE)).
3.2 FC-CBGA (HCTE) Package Description
Figure 3-1 and Figure 3-2 show top and bottom views of the FC-CBGA (HCTE) package, including
pinouts. To conform to JDEC requirements, the package is based on a 23
× 23 position (20 × 20 mm)
layout with the outside perimeter depopulated. Therefore, ball position numbering starts with B2. Signal
names shown in the figures are typically the signal assigned after reset. Signals that are only used during
power-on reset (SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, and CHIP_ID[0–3]) are not
shown in these figures if there is another signal assigned to the pin after reset. Also, there are several
signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ lines that
should be reconfigured by the user. To represent these signals uniquely in the figures, the second
functions (BADDR[29–31], DP[1–7], and INT_OUT) are used.
Table 3-1 lists the MSC8102 signals alphabetically by signal name. Connections with multiple names are
listed individually by each name. Signals with programmable polarity are shown both as signals which
are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin
number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity,
signals with programmable polarity are shown in this table only with their default name (asserted low).
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