參數(shù)資料
型號(hào)： MSC8102M4000
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 75 MHz, OTHER DSP, CBGA431
封裝： 20 X 20 MM, FLIP CHIP, CERAMIC, BGA-431
文件頁(yè)數(shù)： 29/96頁(yè)
文件大?。?/td> 1557K
代理商： MSC8102M4000
2-5
AC Timings
2.6.3 Reset Timing
The MSC8102 has several inputs to the reset logic:
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
All MSC8102 reset sources are fed into the reset controller, which takes different actions depending on
the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table
2-8 describes the reset sources.
Table 2-9 summarizes the reset actions that occur as a result of the different reset sources.
Table 2-8. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8102 and configures various attributes of the MSC8102. On
PORESET, the entire MSC8102 device is reset. SPLL and DLL states are reset, HRESET and SRESET are driven,
the SC140 extended cores are reset, and system configuration is sampled. The clock mode (MODCK bits), reset
configuration mode, boot mode, Chip ID, and use of either a DSI 64 bits port or a System Bus 64 bits port are
configured only when PORESET is asserted.
External Hard
reset
(HRESET)
Input/
Output
Initiates the hard reset flow that configures various attributes of the MSC8102. While HRESET is asserted, SRESET is
also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven, the SC140
extended cores are reset, and system configuration is sampled. The most configurable features are reconfigure.
These features are defined in the 32-bit hard reset configuration word described in Hard Reset Configuration Word
section of the Reset chapter in the MSC8102 Reference Manual.
External Soft
reset
(SRESET)
Input/
Output
Initiates the soft reset flow. The MSC8102 detects an external assertion of SRESET only if it occurs while the
MSC8102 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the SC140
extended cores are reset, and system configuration is maintained.
Software
watchdog reset
Internal
When the MSC8102 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software
watchdog event then generates an internal hard reset sequence.
Bus monitor
reset
Internal
When the MSC8102 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus monitor
event then generates an internal hard reset sequence.
Host reset
command
through the
TAP
Internal
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset signal
and an internal soft reset sequence is generated.
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