參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 100/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
50
Figure 36. Cell Mapping in SONET Frame
The cells are placed in a SONET frame such that the rst cell starts at the rst SPE column of the rst row (145th
column. 144 columns are taken up by TOH). Subsequent cells are placed contiguously, skipping the Transport
OverHead (TOH) columns when appropriate.
The ORSO42G5 and ORSO82G5 supports four cell sizes with varying payloads. The total cell size sent across the
backplane is the combined size of the user cell payload (cell header and data), user BIP and the Link Header byte.
Table 9 indicates the cell sizes supported by the ORSO42G5 and ORSO82G5 within a STS-48c frame. Only one
cell size can be used at a time.
Table 9. ORSO42G5 and ORSO82G5 Supported Cell Sizes
A cell cannot span multiple SONET frames. This implies that there may be some cell sizes for which some bytes
will be unused at the end of a SPE. These are called pad bytes.
Each cell is preceded by a Link Header byte as shown in Figure 37. Table 10 denes the format of the Link Header.
The Link Header byte is useful for cell delineation when cell data are striped across multiple links. The Link Header
is inserted automatically in the transmit direction by the IPC block. The Link Header is checked in the receive direc-
tion and removed by the OPC before the cell is sent across the core/FPGA interface.
Total Cell Size
(Across B/P)
User Cell Payload
Size
(Header/Data)
Link Header
Byte
User BIP Field
Cells/Frame
Number of Pad
Bytes Per SPE
77
75
1
488
8
81
79
1
464
0
85
83
1
442
14
93
91
1
404
12
Note:
To calculate the number of cells per SPE:
[(87Rows/STS-1*9Columns/STS-1)octets/(STS-1 SPE)] * 48 STS-1 = 37584 octets
337584 / TOTAL CELL SIZE = # of cells per SPE.
TO
H
BYTES
A1 A2 J0
Cell 0
Cell 1
Cell 2 (etc.)
Link Header byte
Pad bytes
BYTES
CELL
P
A
YLO
AD
相關(guān)PDF資料
PDF描述
ORSO42G5-3BMN484C IC TRANCEIVERS FPSC 680FPGAM
ORT82G5-1FN680I IC TRANCEIVERS FPSC 680FPBGA
ORT82G5-2FN680I IC TRANCEIVERS FPSC 680FPBGA
VI-J4H-IW-F4 CONVERTER MOD DC/DC 52V 100W
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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