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參數(shù)資料
| 型號(hào)： | ORSO42G5-2BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 84/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
36
aligned together, channels C and D to form a pair as shown in Figure 20. Alternately, all four channels in the SER-
DES blocks can be aligned together to form a communication channel with a bandwidth of 10 Gbps as shown in
Figure 20. Twin Channel Alignment – ORSO42G5
Figure 21. Quad Channel Alignment of SERDES Blocks A and B – ORSO42G5
Individual channels within an alignment group can be disabled (i.e., powered-down) without disrupting other chan-
nels. Note that the SERDES channel that is powered down can not be the source of the RSYSCLKxx that is clock-
ing the read side of the alignment FIFO. When a disabled channel becomes active as part of an alignment group,
the group may need to be re-aligned. Then the whole group needs to be resynched. This would only need to occur
if the transmitting frame pulse for the new link is different from the rest of the group.
Each channel is provided with a 24 word x 33-bit FIFO. The FIFO can perform two tasks: (1) to change the clock
domain from receive clock to a clock from the FPGA side, and (2) to align the receive data over 2 or 4 channels.
This FIFO allows a timing budget of 307 ns that can be allocated to skew between the data lanes and for transfer to
the common clock. The input to the FIFO consists of 32-bit data and a frame pulse that indicates the start of a
frame (or A1A2 framing bytes). This frame pulse is used to synchronize multiple channels within an alignment
group.
If a channel is not in any alignment group, the FIFO control logic will set the FIFO-write-address to the beginning of
the FIFO, and will set the FIFO-read-address to the middle of the FIFO at the rst assertion of frame pulse after
reset or after the resync command.
The RX_FIFO_MIN register bits can be used to control the threshold for minimum unused buffer space in the align-
ment FIFOs between read and write pointers before OVFL status is agged. The synchronization algorithm con-
sists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when a frame pulse
from any channel within an alignment group has been received. The OOS alarm indicates the FIFO is out-of sync
and the channel skew exceeds that which can be handled by the FIFO. Once the frame pulse for all channels within
the alignment group have been received, the count is decremented by 2 until 0 is reached. Data are then read from
the FIFOs and output to the SPE generator before being sent to the FPGA.
For every alignment group, there is an OVFL and OOS status register bit. The OOS bit is agged when the down
counter in the synchronization algorithm has reached a value of 0 and frame pulse from all channels within an
alignment group have not been received. The OVFL bit is agged when the read address at the time of receiving a
Channel AC
Channel AD
Channel BC
Channel BD
Channel AC
Channel AD
t0
t1
OF CHANNELS AC AND AD
TWIN ALIGNMENT
OF CHANNELS BC AND BD
Channel BC
Channel BD
Channel AC
Channel AD
Channel BC
Channel BD
Channel AC
Channel AD
Channel BC
Channel BD
t0
QUAD ALIGNMENT OF CHANNELS AC
, AD, BC, AND BD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORSO42G5-3BMN484C | IC TRANCEIVERS FPSC 680FPGAM |
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
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