參數(shù)資料
型號(hào)： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 5/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
102
30A03
[0]
NO_TX_RDI_EXSEQ
00
Not Transmission of RDI, If
NO_TX_RDI_EXSEQ = 1, a transmit link will
not send data if its corresponding receive link is
not good due to excessive sequence errors. If
this bit is set to 0, a transmit link will still send
data even if its corresponding receive link has
excessive sequence errors. This bit should
always be set during simulation and in SONET
mode.
Both
[1]
AUTO_BUNDLE
Automatic (Link) Bundle, AUTO_BUNDLE = 1
allows a link within a link group to remain active
even when another link within that group is
defective. Cell data from all links within that
group will continue to be sent to the FPGA. If
this bit is set to 0, then all links within a link
group must be good before cell data are read
from the links by the IPC and passed to the
FPGA.
Cell
[2]
RSVD
Reserved
—
[3]
REJOIN_A
Link Rejoin, REJOIN = 1 forces any link in a
SERDES block to reassert a “RX link good” sig-
nal automatically when three consecutive
sequence numbers are correct on that link.
Cell
[4]
AUTO_REMOVE_A
Automatic (Link) Remove, AUTO_REMOVE = 1
indicates that any link in a SERDES block which
sees three excessive sequence errors should
deassert the “RX link good” signal which will
cause the link to be inactive.
Cell
[5]
RSVD
Reserved
—
[6]
REJOIN_B
Link Rejoin, REJOIN = 1 forces any link in a
SERDES block to reassert a “RX link good” sig-
nal automatically when three consecutive
sequence numbers are correct on that link.
Cell
[7]
AUTO_REMOVE_B
AUTO_REMOVE_B = 1 indicates that any link in
SERDES block B which sees three excessive
sequence errors should deassert the “RX link
good” signal which will cause the link to be inac-
tive.
Cell
Table 36. Common Control Register Descriptions – ORSO82G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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