- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11733 > ORSO42G5-2BMN484C (Lattice Semiconductor Corporation)IC TRANCEIVERS FPSC 680FPGAM PDF資料下載
參數(shù)資料
| 型號： | ORSO42G5-2BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 77/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 60 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
3
High-speed SERDES programmable serial data rates of 0.6 Gbps to 2.7 Gbps.
Asynchronous operation per receive channel (separate PLL per channel).
Transmit pre-emphasis (programmable) for improved receive data eye opening.
Provides a 10 Gbps backplane interface to switch fabric using four work and, with the ORSO82G5, four protect
2.5 Gbit/s links. Also supports port cards at rates between 0.6 Gbps and 2.7 Gbps.
Allows wide range of applications for SONET network termination, as well as generic data moving for high-speed
backplane data transfer.
No knowledge of SONET/SDH needed in generic applications. Simply supply data (75 MHz-168.75 MHz clock)
and at least a single frame pulse.
High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
clocks.
Four- or eight-channel HSI functions provide 2.7 Gbps serial user data interface per channel for a total chip
bandwidth of >10Gbps or >20 Gbps (full duplex).
SERDES has low-power CML buffers and support for 1.5V/1.8V I/Os.
SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating
state.
Powerdown option of SERDES HSI receiver and/or transmitter on a per-channel basis.
Ability to mix half-rate and full-rate between the channels with the same reference clock.
Ability to congure each SERDES block independently with its own reference clock.
STS-48 framing in SONET mode.
Programmable enable of SONET scrambler/descrambler, A1/A2 insertion and B1 generation and checking.
Insertion and checking of link assignment values to facilitate interconnection and debugging of backplanes.
Optional AIS-L insertion during loss-of-frame.
Optional RDI-L insertion to indicate remote far-end defects for maintenance capabilities.
SPE signal marks payload bytes in SONET mode.
Frame alignment across multiple ORSO42G5 and ORSO82G5 devices for work/protect switching at STS-
768/STM-256 and above rates.
Supports transparent mode where Transport OverHead (TOH) bytes are user-generated in the FPGA.
Supports two modes of in-band management and conguration with TOH byte extraction/insertion by the
Embedded core. A1/A2 and B1 insertion can be independently enabled.
– AUTO_SOH where the embedded core inserts the A1/A2 framing bytes, performs the B1 calculation and
inserts the B1 byte. All other bytes are passed through unchanged from the FPGA logic as in transparent
mode.
– AUTO_TOH where all of the overhead bytes are set by the embedded core. Most of the bytes are set to zero.
At the receive side, all of the TOH bytes except those set to a non-zero value can be ignored.
Optional A1/A2 corruption, B1 byte corruption, and K2 byte corruption for system debug purposes.
Built-in boundary scan (IEEE 1149.1 and 1149.2 JTAG), including the SERDES interface.
FIFOs align incoming data across all eight channels (ORSO82G5 only), groups of four channels, or groups of
two channels. Optional ability to bypass alignment FIFOs for asynchronous operation between channels is also
provided. (Each channel includes its own recovered clock and frame pulse).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORSO42G5-3BMN484C | IC TRANCEIVERS FPSC 680FPGAM |
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。