參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 69/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
22
Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two
ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency
components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better
power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplies both the signal
and the noise at the receiver.
Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also
degrade the data eye opening at the receiver. In the ORSO42G5 and ORSO82G5, the degree of transmit preem-
phasis can be programmed per channel with two control register bits as shown in Table 4. The high-pass transfer
function of the preemphasis circuit is given by the following equation, where the value of a is shown in Table 4.
H(z) = (1 – az
–1)
Table 4. Preemphasis Settings
SERDES Receive Path
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. Each SERDES receive channel
has its own PLL and this means that the receive clocks are asynchronous between channels. This also enables
each receive channel to either operate in half-rate or full-rate mode.The retimed data are deserialized and pre-
sented as a 8-bit parallel data on the output port. Two-phase receive byte clocks (RBC0 and RBC1) are available
synchronous with the parallel words. RBC0 has its rising edge aligned to the center of the receive byte. RBC1 has
its falling edge aligned to the center of the receive byte. The 8-bit data (LDOUT) as shown in Figure 8, changes on
a single clock edge (rising edge of RBC0 or falling edge of RBC1).
Figure 8. SERDES Receive Path Timing
PE1
PE0
Amount of Preemphasis (a)
0
0% (No Preemphasis, Default)
0
1
12.5%
1
0
12.5%
1
25%
.....
LDOUT[7:0]
RBC0x
RBC1x
q
7
r
1
r
0
s
7
p
3
p
2
p
1
p
0
.....
p
7
p
6
p
5
p
4
r
7
r
6
r
5
r
4
r
3
r
2
s
6
s
5
s
4
s
3
p
HDINx
LDOUT[7:0]
1-bit
8-bit
.....
LATENCY
p
q
r
s
SETUP
HOLD
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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