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參數(shù)資料
| 型號： | ORSO42G5-2BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 65/153頁 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
19
Table 2. Transmit PLL Clock and Data Rates
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. This means that the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as a 8-bit parallel data on
the output port. RWCKx receive byte clocks are divide-by-4 clocks of the RBC (recovered byte clock) clock pro-
vided by the SERDES. This is the clock used in the internal receive functions of the embedded core.
The reference clock is also used by the receive PLL for operation when the input data are not toggling appropri-
ately. Table 3 shows the relationship between the data rates, the reference clock, and the RWCKx clocks.
Table 3. Receive PLL Clock and Data Rates
The differential reference clock is distributed to all channels in a SERDES block. Each channel has a differential
buffer to isolate the clock from the other channels. The input clock is preferably a differential signal; however, the
device can operate with a single-ended input. The input reference clock directly impacts the transmit data eye, so
the clock should have low jitter. In particular, jitter components in the DC-5 MHz range should be minimized.
Detailed Description - SERDES Only Mode
The SERDES only (or bypass) mode is the simplest of the three operating modes for the ORSO42G5 and
ORSO82G5. In this mode, all of the SONET and cell logic block functions are bypassed and data are transferred
directly between the MUX and DEMUX blocks to and from the FPGA interface. This mode is utilized when the user
wants to perform all data processing and uses only the SERDES portion of the Embedded Core. For example, this
mode could be utilized to replace an existing design using stand-alone SERDES and FPGAs.
The basic data paths in the transmit and receive directions are shown in Figure 5. In general, the descriptions in
this section are written to describe the SERDES only mode, although the “SERDES blocks” are also used in
SONET and cell mode operation. At the backplane interface, data are transmitted and received serially over pairs
Data Rate
Reference Clock
TCK78x
Rate
0.6 Gbps
75.00 MHz
18.75 MHz
Half
1.0 Gbps
125.00 MHz
31.25 MHz
Half
1.244 Gbps
155.52 MHz
38.88 MHz
Half
1.35 Gbps
168.75 MHz
42.19 MHz
Half
2.0 Gbps
125.00 MHz
61.50 MHz
Full
2.488 Gbps
155.52 MHz
77.76 MHz
Full
2.7 Gbps
168.75 MHz
84.38 MHz
Full
Notes:
1. The selection of full-rate or half-rate for a given reference clock speed is set by the TXHR
bit in the transmit control register and can be set per channel. (For cell mode all channels
of a group must have the same TXHR selection.)
Data Rate
Reference Clock
RWCKx Clocks
Rate
0.6 Gbps
75.00 MHz
18.75 MHz
Half
1.0 Gbps
125.00 MHz
31.25 MHz
Half
1.244 Gbps
155.52 MHz
38.88 MHz
Half
1.35 Gbps
168.75 MHz
42.19 MHz
Half
2.0 Gbps
125.00 MHz
61.50 MHz
Full
2.488 Gbps
155.52 MHz
77.76 MHz
Full
2.7 Gbps
168.75 MHz
84.38 MHz
Full
Note: The selection of full-rate or half-rate for a given reference clock speed is set by the
RXHR bit in the receive control register and can be set per channel. (For cell mode all chan-
nels of a group must have the same RXHR selection).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
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