參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 144/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
90
30A05
[0:2]
ERRCNT_CH
00
Error Count Channel Select, Control bits to
select which channel’s Section B1 error and Cell
BIP error counts are recorded by the
BIP_ERR_CNT and CELL_BIP_ERR_CNT reg-
isters.
“010” - Channel AC,
“011” - Channel AD,
“110” - Channel BC,
“111” - Channel BD
Both
[3]
RSVD
Reserved
—
[4]
CELL_MODE_A2
Cell Mode Enable, CELL_MODE_A2 = 1
enables cell mode for the channel group AC and
AD.
Cell
[5]
RSVD
Reserved
—
[6]
CELL_MODE_B2
Cell Mode Enable, CELL_MODE_B2 = 1
enables cell mode for the channel group BC and
BD.
Cell
[7]
RSVD
Reserved
—
30A06
[0:4]
RSVD
00
Reserved
—
[5:6]
RESET_PHASE
Reset Phase, Two bits to select delay phase for
delaying the soft reset bit SOFT_RESET with
respect to the synchronizing clock. Four delay
phases can be selected through the values “00”,
“01”, “10” and “11”.
Both
[7]
SOFT_RESET
Soft Reset, SOFT_RESET=1 resets the embed-
ded core ip ops except for the software regis-
ters. This bit does not affect the state of the
registers inside the SERDES blocks.
Both
30A07
[0:6]
RSVD
00
Reserved
—
[7]
TX_CFG_DONE
Transmitter Conguration Done, Edge sensitive
bit to indicate that all TX conguration bits are
set. After all register bits have been set for
Transmit direction, write a 0 and then a 1 to this
bit.
Cell
30A08
[0]
ALARM_STATUS_BD
00
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BD. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[1]
ALARM_STATUS_BC
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel BC. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[2:3]
RSVD
Reserved
—
[4]
ALARM_STATUS_AD
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AD. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[5]
ALARM_STATUS_AC
Alarm Status Indicator, This bit is an OR of all
alarm status bits for the channel AC. A 1 on this
bit will also set the alarm pin on the system bus
interrupt cause register (on the FPGA side).
Both
[6:7]
RSVD
Reserved
—
Table 28. Common Control Register Descriptions – ORSO42G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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