參數(shù)資料
型號: ORSO42G5-2BMN484C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 16/153頁
文件大?。?/td> 0K
描述: IC TRANCEIVERS FPSC 680FPGAM
產品變化通告: Product Discontinuation 01/Aug/2011
標準包裝: 60
系列: *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
112
External Reference Clock
The external reference clock selection and its interface are a critical part of system applications for this product.
Table 46 species reference clock requirements, over the full range of operating conditions. The designer is
encourage to read TN1040, SERDES Reference Clock, which discusses various aspects of this system element
and its interconnection.
Table 46. Reference Clock Specications (REFCLKP_[A:B] and REFCLKN_[A:B])
Parameter
Min.
Typ.
Max.
Units
Frequency Range
60
185
MHz
Frequency Tolerance
1
-350
350
ppm
Duty Cycle (Measured at 50% Amplitude Point)
40
50
60
%
Rise Time
500
1000
ps
Fall Time
500
1000
ps
P–N Input Skew
75
ps
Differential Amplitude
500
800
2 x VDDIB
mVp-p
Common Mode Level
Vsingle-ended/2
0.75
VDD15 – (Vsingle-ended/2)
V
Single-Ended Amplitude
250
400
VDDIB
mVp-p
Input Capacitance (at REFCLKP_[A:B])
5
pF
Input Capacitance (at REFCLKN_[A:B])
5
pF
1. This specication indicates the capability of the high speed receiver CDR PLL to acquire lock when the reference clock frequency and
incoming data rate are not synchronized.
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