參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 152/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
98
30806 - AA
30816 - AB
30826 - AC
30836 - AD
30906 - BA
30916 - BB
30926 - BC
30936 - BD
[0:5]
RSVD
00
Reserved
—
[6]
AUTO_B1_xx
AUTO_B1_xx = 0, B1 is not inserted by the
embedded core
AUTO_B1_xx = 1, B1 is calculated and inserted
by the embedded core
AUTO_TOH_xx = 1 overrides this bit
Both
[7]
AUTO_A1A2_xx
AUTO_A1A2_xx = 0, A1/A2 bytes are not
inserted by the embedded core
AUTO_A1A2_xx = 1, A1/A2 bytes inserted by
the embedded core
AUTO_TOH_xx = 1 overrides this bit
Table 35. Per-Channel Status Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
Channel Status Registers (Read Only) xx = [AA,...,BD]
30808 - AA
30818 - AB
30828 - AC
30838 - AD
30908 - BA
30918 - BB
30928 - BC
30938 - BD
[0:4]
RSVD
00
Reserved
—
[5]
CELL_ALIGN_ERR_xx
Cell Alignment Error, CELL_ALIGN_ERR = 1
indicates that the internal transmit frame pro-
cessor did not detect a start of cell indicator
when it was expecting a new cell. If the corre-
sponding alarm enable bit has been set, a 1 on
this bit will cause an alarm.
Cell
[6]
TX_URUN_ERR_xx
Transmit Underrun Error, TX_URUN_ERR = 1
indicates an underrun error in the transmit
Asynchronous FIFO. If the corresponding alarm
enable bit has been set, a 1 on this bit will cause
an alarm.
Cell
[7]
TX_ORUN_ERR_xx
Transmit Overrun Error, TX_ORUN_ERR = 1
indicates an overrun error in the transmit Asyn-
chronous FIFO. The TX FIFO is designed to not
overow since it sends backpressure signal to
the FPGA when it cannot accept more cells. If
the corresponding alarm enable bit has been
set, a 1 on this bit will cause an alarm.
Cell
Table 34. Per-Channel Control Register Descriptions – ORSO82G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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